Method and apparatus for built-in self test of integrated circuits
US6085346A · kind A · utility
42Cited by
1References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 3, 1996 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Sep 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also including the ability to test a plurality of embedded memories at full speed in parallel. Testing the memories at full speed both reduces test time and improves the quality of the testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.