Method for fabricating a very dense chip package
US6087199A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Feb 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m<G.ltoreq.100 .mu.m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.