Composite semiconductor gate dielectrics

US6087229A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Sheldon Aronowitz · San Jose, US
• David Chan · San Jose, US
• James Kimball · San Jose, US
• David Lee · Sunnyvale, US
• John Haywood · Santa Clara, US
• Valeriy Sukharev · Cupertino, US

Key dates

• Filing date: Mar 9, 1998
• Grant date: Jul 11, 2000
• Expiry date: Mar 9, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.