Dual damascene
US6087252A · kind A · utility
5Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form in a self-aligned process. Therefore, it can successfully avoid misalignment while forming a via plug and an interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.