Semiconductor device having lower minority carrier noise
US6087691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 7, 1997 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | May 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
Abstract
On a p.sup.++ substrate (1) provided is a p.sup.- epitaxial layer (2) having an impurity concentration lower than that of the p.sup.++ substrate (1). A p well (3) is formed in a portion of the p.sup.- epitaxial layer 2 and further n.sup.+ diffusion layers (4a and 4b) are selectively formed in the p well (3). A memory cell capacitor (5) is connected onto the n.sup.+ diffusion layer 4b. On the other hand, an no diffusion layer (6) is selectively formed in the p.sup.- epitaxial layer (2) separately from the p well (3), to which an external signal input circuit (7) is connected. Further, a p.sup.++ diffusion layer 9a is provided between the external signal input circuit (7) serving as a source for injection of the minority carriers, i.e., electrons and the n.sup.+ diffusion layer (4b) connected to the memory cell capacitor (5), for blocking the entry of the minority carries. The p.sup.++ diffusion layer (9a) extends up to such a depth as to reach the p.sup.++ substrate (1) from a surface of the p.sup.- epitaxial layer (2). Having this structure, a semiconductor device which does not allow the electrons injected to the p.sup.- epitaxial layer from the external signal input circuit to re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.