Method and apparatus for configuring a semiconductor device for compatibility with multiple logic interfaces
US6087851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017581
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device can be configured for compatibility with different system level interfaces, e.g., LVTTL or SSTL, after assembly, thereby eliminating the need for bonding options and reducing the cost of manufacturing the device. The device includes an interface dependent circuit that operates with a selected interface in response to one or more interface enable signals. Several alternative embodiments include interface control circuits and mode register circuits for generating the interface enable signals responsive to a row address and control signals such as RAS, CAS, WE, and CS. Some embodiments also include a switching network that allows an input buffer to use an internally generated reference voltage for one interface and an externally applied reference voltage for a second interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.