Chi-Wook Kim
28Patents
8h-index
32Co-inventors
71Inventor score
Filing activity: Apr 30, 1998 → Aug 9, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6526473B1 | Memory module system for controlling data input and output by connecting selected memory modules to a data line | Physics | 103 | Expired |
| US6525988B2 | Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same | Electricity | 64 | Expired |
| US6324119A | Data input circuit of semiconductor memory device | Physics | 48 | Expired |
| US6087851A | Method and apparatus for configuring a semiconductor device for compatibility with multiple logic interfaces | Electricity | 11 | Expired |
| US7161823B2 | Semiconductor memory device and method of arranging signal and power lines thereof | Physics | 11 | Expired |
| US6795372B2 | Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages | Physics | 10 | Expired |
| US7038972B2 | Double data rate synchronous dynamic random access memory semiconductor device | Physics | 9 | Expired |
| US6898139B2 | Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation | Physics | 9 | Expired |
| US6236619A | Synchronous dynamic random access memory semiconductor device having write-interrupt-write function | Physics | 6 | Expired |
| US7057446B2 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level | Physics | 5 | Expired |
| US7084684B2 | Delay stage insensitive to operating voltage and delay circuit including the same | Electricity | 5 | Expired |
| US7184347B2 | Semiconductor memory devices having separate read and write global data lines | Physics | 5 | Expired |
| US7317645B2 | Redundancy repair circuit and a redundancy repair method therefor | Physics | 3 | Expired |
| US7110316B2 | Shared decoupling capacitance | Physics | 3 | Expired |
| US9824946B2 | Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level | Electricity | 2 | Active |
| US7336518B2 | Layout for equalizer and data line sense amplifier employed in a high speed memory device | Physics | 2 | Expired |
| US7068083B2 | Synchronous output buffer, synchronous memory device and method of testing access time | Physics | 2 | Expired |
| US7298199B2 | Substrate bias voltage generating circuit for use in a semiconductor memory device | Physics | 2 | Expired |
| US7355901B2 | Synchronous output buffer, synchronous memory device and method of testing access time | Physics | 2 | Expired |
| US7495472B2 | Circuits/methods for electrically isolating fuses in integrated circuits | Physics | 2 | Active |
| US7525858B2 | Semiconductor memory device having local sense amplifier | Physics | 2 | Active |
| US6229756A | Semiconductor memory device capable of preventing mis-operation due to load of column address line | Physics | 1 | Expired |
| US6777987B2 | Signal buffer for high-speed signal transmission and signal line driving circuit including the same | Electricity | 1 | Expired |
| US7075849B2 | Semiconductor memory device and layout method thereof | Physics | 1 | Expired |
| US7352646B2 | Semiconductor memory device and method of arranging a decoupling capacitor thereof | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.