Method and circuit for measuring the read operation delay on DRAM bit lines
US6088273A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1999 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for measuring the read operation delay on DRAM bit lines are disclosed. The circuit comprises a plurality of circuit blocks connected in series, each having a 1-bit DRAM cell. The output of the DRAM cell in each circuit block is connected to the word line of the DRAM cell of the next circuit block through inverters, so the read operation in the DRAM cell of the next circuit block is triggered. The total delay between the word line at the first circuit block and the output of the last circuit block can be measured on the oscilloscope. The delay for every 1-bit DRAM cell is equal to the total delay divided by the number of circuit blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.