Fast 16 bit, split transaction I/O bus
US6088370A · kind A · utility
3Cited by
24References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1997 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Sep 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.