Multiprocessor cache coherence directed by combined local and global tables
US6088769A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.