Read/write timing for maximum utilization of bidirectional read/write bus
US6088774A · kind A · utility
107Cited by
7References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.