Computer system with low power mode invoked by halt instruction
US6088807A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.