Method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US6090648A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Aug 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a self-aligned, integrated resistor load on ultrathin silicon on sapphire film, with the method being used to manufacture an FET and a resistor load. While the film can be used, for example, to manufacture a four transistor SRAM, it is not limited to such applications. The method encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from, and integral with, the ultra thin silicon material, it can be automatically self-aligned to the transistor. The self-aligned, integrated resistor loads are comprised of an insulating substrate, with a layer of silicon formed on the insulating substrate. The self-aligned resistor loads are integrally formed in the same film as the transistors and thereby require no second layer of deposited material such as polysilicon. The layer over the substrate additionally provides improved heat sinking capability, as well as a diffusion barrier which enables the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.