Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances
US6090650A · kind A · utility
20Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.