Etchstop for integrated circuits
US6090697A · kind A · utility
71Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-selectivity via etching process. The process includes the steps of: forming an etchstop layer 840 of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; forming a dielectric layer over the etchstop layer; and etching the dielectric layer with a fluorine-bearing etchant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.