Method of fabricating a field effect transistor
US6090716A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
Abstract
In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas. An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas. A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas. A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.