Process for fabricating a semiconductor structure having a self-aligned spacer
US6090722A · kind A · utility
11Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.