Inventor · Beacon, NY, US

Richard S. Wise

93Patents
12h-index
141Co-inventors
87Inventor score

Filing activity: Aug 15, 1997 → Jun 17, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7288482B2 Silicon nitride etching methods Electricity 247 Expired
US7859013B2 Metal oxide field effect transistor with a sharp halo Electricity 99 Active
US7476578B1 Process for finFET spacer formation Electricity 42 Active
US8426300B2 Self-aligned contact for replacement gate devices Electricity 34 Active
US6051504A Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma Electricity 21 Expired
US6355567B1 Retrograde openings in thin films Electricity 19 Expired
US6869542B2 Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials Electricity 15 Expired
US6461529B1 Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme Electricity 15 Expired
US6541320B2 Method to controllably form notched polysilicon gate structures Electricity 15 Expired
US6342722B1 Integrated circuit having air gaps between dielectric and conducting lines Electricity 15 Expired
US6838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal Electricity 14 Expired
US7691701B1 Method of forming gate stack and structure thereof Electricity 13 Active
US7943457B2 Dual metal and dual dielectric integration for metal high-k FETs Electricity 11 Active
US6345399B1 Hard mask process to prevent surface roughness for selective dielectric etching Emerging Cross-Sectional Technologies 11 Expired
US6090722A Process for fabricating a semiconductor structure having a self-aligned spacer Electricity 11 Expired
US8008160B2 Method and structure for forming trench DRAM with asymmetric strap Electricity 10 Active
US8018005B2 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs Electricity 10 Active
US8507375B1 Alignment tolerant semiconductor contact and method Electricity 9 Active
US6903023B2 In-situ plasma etch for TERA hard mask materials Electricity 8 Expired
US9530665B2 Protective trench layer and gate spacer in finFET devices Electricity 8 Active
US7498271B1 Nitrogen based plasma process for metal gate MOS device Electricity 7 Active
US6953724B2 Self-limited metal recess for deep trench metal fill Electricity 7 Expired
US8759172B2 Etch stop layer formation in metal gate process Electricity 7 Active
US7892928B2 Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers Electricity 7 Active
US9391020B2 Interconnect structure having large self-aligned vias Electricity 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.