Quantum WELL MOS transistor and methods for making same
US6091076A · kind A · utility
80Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Feb 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/165
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the source and drain areas is separated from the substrate by an electrically insulating layer that is sufficiently thick to prevent charge carriers from passing through this insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.