Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips
US6091094A · kind A · utility
29Cited by
9References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.