Thomas Rupp
18Patents
7h-index
51Co-inventors
69Inventor score
Filing activity: Mar 25, 1998 → Aug 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6258659A | Embedded vertical DRAM cells and dual workfunction logic gates | Electricity | 37 | Expired |
| US6172390A | Semiconductor device with vertical transistor and buried word line | Electricity | 31 | Expired |
| US6091094A | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips | Electricity | 29 | Expired |
| US6291335A | Locally folded split level bitline wiring | Electricity | 23 | Expired |
| US6274440A | Manufacturing of cavity fuses on gate conductor level | Electricity | 20 | Expired |
| US6153902A | Vertical DRAM cell with wordline self-aligned to storage trench | Electricity | 18 | Expired |
| US6204187A | Contact and deep trench patterning | Electricity | 14 | Expired |
| US6960523B2 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Electricity | 7 | Expired |
| US6444531B1 | Disposable spacer technology for device tailoring | Electricity | 5 | Expired |
| US6268293A | Method of forming wires on an integrated circuit chip | Electricity | 4 | Expired |
| US6486505B1 | Semiconductor contact and method of forming the same | Electricity | 3 | Expired |
| US6096664A | Method of manufacturing semiconductor structures including a pair of MOSFETs | Electricity | 3 | Expired |
| US6210995A | Method for manufacturing fusible links in a semiconductor device | Electricity | 3 | Expired |
| US6699750B1 | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips | Electricity | 3 | Expired |
| US6255158A | Process of manufacturing a vertical dynamic random access memory device | Electricity | 2 | Expired |
| US11764176B2 | Semiconductor device including bonding pad metal layer structure | Electricity | 0 | Active |
| US12183696B2 | Semiconductor device including bonding pad metal layer structure | Electricity | 0 | Active |
| US11329126B2 | Method of manufacturing a superjunction semiconductor device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.