Method and apparatus for protecting gate oxide from process-induced charging effects

US6091114A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Homi Mogul · Dallas, US
• Joe W. McPherson · Plano, US
• Bob D. Strong · Garland, US
• Anand Seshadri · Plano, US

Key dates

• Filing date: Mar 31, 1998
• Grant date: Jul 18, 2000
• Expiry date: Mar 31, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

A semiconductor device includes a first transistor (52) and gated diode (50) formed at a face of a semiconductor layer (56). The first transistor (52) includes a source region (60a), a drain region (60b), a gate oxide layer (62), and a conductive gate (64). The gated diode (54) includes a first moat region (66a), a second moat region (66b), a gate oxide layer (68), and a conductive gate (70). A first conductor (77) connects the conductive gate (70) of the gated diode (54) to the semiconductor layer (56) and a second conductor (76) connects the moat regions (66a, 66b) of the gated diode (54) to the conductive gate (64) of the first transistor (52). Gated diode (54) has a reduced breakdown voltage relative to the gate oxide layer (62) of first transistor (52) and thus establishes a leakage path to semiconductor layer (56) to direct leakage current to semiconductor layer (56), thereby inhibiting charge from accumulating on the gate oxide layer (62) of first transistor (52).