Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices
US6091642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1999 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.