Synchronous burst semiconductor memory device with parallel input/output data strobe clocks
US6091663A · kind A · utility
27Cited by
5References
32Claims
0Family size
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Key dates
| Filing date | Aug 20, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Aug 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous burst semiconductor memory device operating in synchronism with at least one external clock signal and capable of accessing data on every edge of the external clock signal is provided. The burst memory device includes a clock generator for generating a number of data output/input strobe clock signals synchronized with the external clock signal in response to a plurality of input information signals, and a data-out/in buffer for outputting/inputting internal/external data in synchronism with the data output/input strobe clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.