Implementation of configurable on-chip fast memory using the data cache RAM
US6092159A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | May 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or unlocking of individual cache lines in the data cache. A locked cache line is not subject to deallocation. By locking a plurality of lines in the data cache, the microprocessor configures a reserved area of guaranteed fast access memory within the data cache. The data cache includes a mechanism to disable write-through of write requests on a line addressable basis. By executing a software write-through disable instruction, the microprocessor commands the data cache to disable write through operations on an individual cache line. By disabling write-through on cache lines which have been locked, the plurality of locked lines behaves like a true fast-access internal memory with guaranteed access time: write requests targeting the reserved area of locked lines are not written through to the bus interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.