Processor and instruction set with predict instructions
US6092188A · kind A · utility
41Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.