Michael Corwin
27Patents
18h-index
42Co-inventors
77Inventor score
Filing activity: Oct 13, 1997 → Apr 9, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7908259B2 | Hardware accelerated reconfigurable processor for accelerating database operations and queries | Physics | 126 | Active |
| US7966343B2 | Accessing data in a column store database based on hardware compatible data structures | Physics | 119 | Active |
| US6016542A | Detecting long latency pipeline stalls for thread switching | Physics | 82 | Expired |
| US6550001B1 | Method and implementation of statistical detection of read after write and write after write hazards | Physics | 78 | Expired |
| US8244718B2 | Methods and systems for hardware acceleration of database operations and queries | Physics | 65 | Active |
| US7110394B1 | Packet switching apparatus including cascade ports and method for switching packets | Electricity | 62 | Expired |
| US6240510A | System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions | Physics | 51 | Expired |
| US6304960A | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions | Physics | 43 | Expired |
| US6092188A | Processor and instruction set with predict instructions | Physics | 41 | Expired |
| US7606968B2 | Multi-level content addressable memory | Physics | 35 | Active |
| US6611910B2 | Method for processing branch operations | Physics | 33 | Expired |
| US6591359B1 | Speculative renaming of data-processor registers | Physics | 28 | Expired |
| US6985975B1 | Packet lockstep system and method | Physics | 26 | Expired |
| US8229918B2 | Hardware accelerated reconfigurable processor for accelerating database operations and queries | Physics | 26 | Active |
| US6237077A | Instruction template for efficient processing clustered branch instructions | Physics | 24 | Expired |
| US8224800B2 | Hardware accelerated reconfigurable processor for accelerating database operations and queries | Physics | 21 | Active |
| US8234267B2 | Hardware accelerated reconfigurable processor for accelerating database operations and queries | Physics | 21 | Active |
| US9141670B2 | Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators | Physics | 18 | Active |
| US6438650B1 | Method and apparatus for processing cache misses | Physics | 15 | Expired |
| US6438682B1 | Method and apparatus for predicting loop exit branches | Physics | 11 | Expired |
| US9542442B2 | Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns | Physics | 9 | Active |
| US8862625B2 | Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns | Physics | 8 | Active |
| US6378063B2 | Method and apparatus for efficiently routing dependent instructions to clustered execution units | Physics | 7 | Expired |
| US9378231B2 | Accessing data in column store database based on hardware compatible data structures | Physics | 4 | Active |
| US10803066B2 | Methods and systems for hardware acceleration of database operations and queries for a versioned database based on multiple hardware accelerators | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.