Semiconductor memory apparatus having refresh test circuit
US6094389A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus having a refresh test circuit provided with a control unit, a write control unit, a row address buffer and column address buffer, a refresh address counter, a refresh control unit, a column decoder, a data input/output buffer, a plurality of sense amplifier arrays and a plurality of memory cell arrays, includes a refresh test control unit for receiving an address signal by the control of the control unit and controlling the refresh control unit, the row block decoder and the plurality of sense amplifier arrays. The apparatus screens refresh-related poor products by efficiently applying a disturb refresh test during a short period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.