Cache coherence for lazy entry consistency in lockup-free caches
US6094709A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1997 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Jul 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing false sharing in a shared memory system by enabling two caches to modify the same line at the same time. More specifically, with this invention a lock associated with a segment of shared memory is acquired, where the segment will then be used exclusively by processor of the shared memory system that has acquired the lock. For each line of the segment, an invalidation request is sent to a number of caches of the system. When a cache receives the invalidation request, it invalidates each line of the segment that is in the cache. When each line of the segment is invalidated, an invalidation acknowledgement is sent to the global directory. For each line of the segment that has been updated or modified, the update data is written back to main memory. Then, an acquire signal is sent to the requesting processor which then has exclusive use of the segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.