Method for controlling the thickness of a passivation layer on a semiconductor device
US6096579A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for controlling the thickness of a passivation layer underlying with a fuse on a semiconductor device is disclosed herein. The anti-reflective coating on a metal layer is buried in the passivation layer, and the fuse is in a semiconductor device. The method includes the following steps. First, use a first etchant and Ar to etch the passivation layer till the anti-reflective coating is exposed, the first thickness of the passivation layer above the anti-reflective coating is smaller than the second thickness of the passivation layer above the fuse. Then, utilize a second etchant to etch the anti-reflective coating till the metal layer is exposed. The second etchant has a selectivity ratio from the anti-reflective coating to the passivation layer being at least 10. The second etchant mentioned above includes BCl.sub.3, Cl.sub.2, O.sub.2, and Ar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.