Method to fabricate dual threshold CMOS circuits
US6096611A · kind A · utility
137Cited by
11References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
The method for forming dual threshold circuits on a semiconductor substrate is provided. The semiconductor substrate has a first region, a second region, and a third region. The first region, the second region, and the third region are doped with first type dopants. Then the first region and the second region are doped with second type dopants. The second type dopants are opposite type dopants of the first type dopants. The semiconductor substrate can be performed with more steps to form transistors in the first region, the second region, and the third region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.