Fabrication method of semiconductor device using CMP process
US6096632A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/03
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method of a semiconductor device is provided, which eliminates the effects of polishing residue generated by a CMP process. A first layer having a hole is prepared, where the first layer may be formed directly on a surface of a semiconductor substrate or formed over a surface of a semiconductor substrate through at least one layer. A second layer is then formed to cover the hole. The hole is not filled with the second layer to thereby form a gap on the second layer. A protection layer is formed on the second layer so that the gap is filled with the protection layer. The protection layer and the second layer are removed by a CMP process until the first layer is exposed, thereby selectively leaving the protection layer and the second layer in the hole. The second layer left in the hole serves as a plug. A third layer is formed on the second layer to cover the plug. Preferably, a step of selectively removing the protection layer left in the gap is additionally provided prior to the CMP process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.