Dynamic random access memory cell suitable for integration with semiconductor logic devices

US6097048A · kind A · utility

Assignee

• OKI Semiconductor Co., Ltd. · JP

Inventors

• Chingchi Yao · Saratoga, US
• Chung-Jen Chien · Saratoga, US
• Thomas Chao · Cupertino, US

Key dates

• Filing date: Dec 22, 1998
• Grant date: Aug 1, 2000
• Expiry date: Dec 22, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/50

Abstract

A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.