Semiconductor device and manufacturing method thereof
US6097064A · kind A · utility
11Cited by
1References
83Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/815
Abstract
An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is aimed. An IC having a high ESD immunity is realized by causing a surface concentration of N type impurities in a drain area of an N-channel type MOS transistor to be more than 5 E 18/cm.sup.3 in maximum in the direction of gate electrode of a gate electrode terminal and to have a monotonous concentration profile in which there is no kink in a portion less than 5 E 18/cm.sup.3 in the surface direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.