Symmetrical NOR gates
US6097222A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A NOR gate including a pull-down circuit coupled to a pull-up circuit. The NOR gate is configured to drive an output signal to a low logic state at a substantially uniform slew rate regardless of the number of input signals that are in high logic state. The pull-down circuit may include a first plurality of transistor circuits each coupled to a corresponding one of the plurality of input signals, and a second plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The first and second plurality of transistor circuits may each include an n-channel MOS (NMOS) transistor. The NOR gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the set-up and hold time window of the input path circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.