Multi-level memory circuit with regulated writing voltage
US6097628A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1999 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Jun 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.