Dynamic single bit per cell to multiple bit per cell memory
US6097637A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1996 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Sep 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.