Patent · US Expired

Pointer circuit with low surface requirement high speed and low power loss

US6097661A · kind A · utility

0Cited by
1References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 25, 1998
Grant dateAug 1, 2000
Priority date
Expiry dateSep 25, 2018

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C8/04
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.