"Lock protocol for PCI bus using an additional ""superlock"" signal on the system bus"
US6098134A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immedi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.