Christopher J. Pettey
73Patents
22h-index
29Co-inventors
88Inventor score
Filing activity: Jun 5, 1996 → Oct 25, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6134638A | Memory controller supporting DRAM circuits with different operating speeds | Physics | 187 | Expired |
| US6594712B1 | Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link | Physics | 136 | Expired |
| US7979592B1 | Virtualization bridge device | Physics | 95 | Active |
| US5870567A | Delayed transaction protocol for computer system bus | Physics | 84 | Expired |
| US7188209B2 | Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets | Physics | 78 | Expired |
| US7149819B2 | Work queue to TCP/IP translation | Electricity | 74 | Expired |
| US7149817B2 | Infiniband TM work queue to TCP/IP translation | Electricity | 72 | Expired |
| US7046668B2 | Method and apparatus for shared I/O in a load/store fabric | Physics | 65 | Expired |
| US7457906B2 | Method and apparatus for shared I/O in a load/store fabric | Physics | 64 | Expired |
| US7219183B2 | Switching apparatus and method for providing shared I/O within a load-store fabric | Electricity | 61 | Expired |
| US6266731A | High speed peripheral interconnect apparatus, method and system | Physics | 59 | Expired |
| US5835741A | Bus-to-bus bridge in computer system, with fast burst memory range | Physics | 47 | Expired |
| US7103064B2 | Method and apparatus for shared I/O in a load/store fabric | Electricity | 43 | Expired |
| US7174413B2 | Switching apparatus and method for providing shared I/O within a load-store fabric | Electricity | 40 | Expired |
| US7493416B2 | Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture | Physics | 39 | Active |
| US6098134A | "Lock protocol for PCI bus using an additional ""superlock"" signal on the system bus" | Physics | 37 | Expired |
| US6557068B2 | High speed peripheral interconnect apparatus, method and system | Physics | 33 | Expired |
| US6021480A | Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line | Physics | 30 | Expired |
| US5872941A | Providing data from a bridge to a requesting device while the bridge is receiving the data | Physics | 28 | Expired |
| USRE37980E1 | Bus-to-bus bridge in computer system, with fast burst memory range | General | 26 | Expired |
| US7401126B2 | Transaction switch and network interface adapter incorporating same | Electricity | 24 | Expired |
| US6055590A | Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size | Physics | 22 | Expired |
| US10223317B2 | Configurable logic platform | Physics | 21 | Active |
| US8346884B2 | Method and apparatus for a shared I/O network interface controller | Electricity | 19 | Active |
| US7664909B2 | Method and apparatus for a shared I/O serial ATA controller | Physics | 18 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.