System for completing instruction out-of-order which performs target address comparisons prior to dispatch
US6098168A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Mar 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.