System to fix post-layout timing and design rules violations
US6099584A · kind A · utility
209Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1996 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Dec 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.