LDD structure for ESD protection and method of fabrication
US6100125A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Sep 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted. The resistivity of those resistive LDD regions is greater than the resistivity of the adjacent portions of the drain region. The result is more uniform turn-on of ESD transistor fingers in a protection device set without the need to a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.