Method for fabricating a via
US6100183A · kind A · utility
14Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Aug 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.