Tunable threshold SOI device using back gate and intrinsic channel region
US6100567A · kind A · utility
57Cited by
1References
6Claims
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Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In a fully depleted SOI device having a back gate structure, the channel region of the device is formed of an intrinsic or pseudo-intrinsic semiconductor. This has the effect of reducing an unbiased threshold of the device, as well as substantially reducing threshold variations normally associated with variations in dopant concentrations, while providing a means to electrically tune the threshold voltage by adjusting a potential applied to the back gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.