Structure of a bonding pad for semiconductor devices
US6100573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a structure of a bonding pad, which comprising: a substrate; a dielectric layer formed over the substrate; a first metal layer formed in the dielectric layer; a second metal layer formed in the dielectric layer and above the first metal layer; a plurality of first plugs formed between the first metal layer and the second metal layer, wherein the plugs are used for connecting the first metal layer with the second metal layer; a third metal layer formed over the dielectric layer; and a plurality of second plugs, formed between the second metal layer and the third metal layer, wherein the second plugs are used for connecting the second metal layer with the third metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.