Low capacitance multilevel metal interconnect structure and method of manufacture
US6100590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Nov 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low capacitance multilevel metal interconnect structure for use in integrated circuits that provides for increased IC device speed and that includes a plurality of patterned metal layers separated and supported by an interconnect dielectric material. The low capacitance multilevel metal interconnect structure has interconnect structure related capacitance lowering gaps in the interconnect dielectric material with the gaps, adjoining at least one of the patterned metal layers. While the gaps adjoin at least the uppermost patterned metal layer, they can also extend downward through the interconnect dielectric material such that they also adjoin one or more patterned metal layers that underlie the uppermost patterned metal layer. A process for the manufacture of the low capacitance multilevel metal interconnect structure includes a step of removing interconnect dielectric material from a conventional multilevel metal interconnect structure to form gaps adjoining at least one of the patterned metal layers. The gaps are formed without removing a substantial amount of interconnect dielectric material from directly underneath any patterned metal layer. This removal can be accomplished w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.