Bias stabilization circuit
US6100753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Aug 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/245
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.