Multi-level memory circuit with regulated reading voltage
US6101121A · kind A · utility
12Cited by
2References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 5, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | May 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A read voltage generating circuit is adapted to an input supply voltage and provides a read voltage to the memory cells. The read voltage generating circuit includes a voltage boosting circuit providing the read voltage greater than the input supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.