System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data
US6101329A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the current invention, there is provided a system for transferring data into and out of a first-in, first-out (FIFO) data buffer. The buffer has a read pointer and a write pointer. The system comprises a comparator circuit, multiple counter blocks, and multiple flag registers. The counter blocks and flag registers are connected to a system clock to provide timing information and capacity indications to the comparator. The comparator circuit continuously monitors the multiple counter blocks, thereby tracking buffer pointer positions. The flag registers indicate relative buffer capacity and provide early indication to the system that the buffer is almost full or almost empty in appropriate conditions. The comparator circuit continuously evaluates the read and write counter blocks and the flag registers to determine the ability of the buffer to accept or transmit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.